The present invention concerns design and manufacturing of integrated circuits and pertains particularly to an accurate timing model for logic simulation of integrated circuits which utilizes tabular timing models.
When designing an integrated circuit, it is generally desirable to simulate the fimctioning of logic circuitry within the integrated circuit. In order to accurately access the performance of the circuitry, it is desirable that the logic simulation of logic include an accurate assessment of timing delays through the circuitry, at least in the critical paths.
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances.
When developing a timing model, it is important, therefore, to take into account the time delay introduced by charging and discharging the input capacitance of logic cells. This time delay is directly affected by the input current available to charge or discharge the input capacitance to the logic cell. This input current, in turn, is directly affected by the fan out of the output of the logic cell providing the input current.
Timing models for logic circuits are often stored in a cell library used to design the logic circuit. The timing model is used in event driven simulation and synthesis of circuits constructed from the elements of the library. The timing model generally describes the cell delay between each input pin and output pin transition. There is often a separate timing model for each cell in the library.
For submicron circuits, an accurate cell delay model generally depends upon the ramp (or transition time) of the input pin for each cell in the library. The ramp is the time it takes for the voltage of the node to pass between two pre-specified values. Generally, the model also describes the ramp of the output pin. The output ramp model depends upon the load on the output pin. In addition, for some cells, the output ramp model also depends upon the input ramp.
In some commercial simulators and synthesizers the cell delay and output ramp models are stored in the form of tables. For example, this is done in a Design Compiler from Synopsis. In such a tabular cell delay model, the information is stored in a list of input ramp indices (ir.sub.1, ir.sub.2, ir.sub.3, ir.sub.4, . . ., ir.sub.m), a list of output load indices (c.sub.1, c.sub.2, c.sub.3, c.sub.4, . . ., c.sub.n) and an "m" by "n" array of cell delay values. For each input ramp index and each load index, there is listed an output ramp and a cell delay. This is done, for example, in a separate table each for the output ramp and the cell delay. Depending upon the implementation, the input ramp indices and the output load indices may or may not be shared by the table for the output ramp and the table for the cell delay. For cells where the output ramp does not depend upon the input ramp, the table for the output ramp is simplified so that for each load index there is listed an output ramp.
The particular values chosen for the indices may vary depending upon the cell used. Also, for a particular cell, the particular values chosen for the indices may vary depending upon the input pin/output pin combination which a particular table represents.
When a circuit is constructed from elements of the cell library and then simulated, the cell delays and output ramps for each cell instance are calculated from three criteria. The first criteria is the cell delay and output ramp models for the cell. This is essentially the tables described above. The second criteria is the load(s) on the output pin(s) of the cell instance. This is obtained from the capacitances of the output node wires and the input capacitances of subsequent cells driven by the output pin(s), This information is contained in the netlist of the circuit. The third criteria is the ramp(s) of the input pin(s) of the cell instance. These are equal to the output ramps of the cell instances driving the input pins of the cell instance.
When the timing models are stored in table format, the value of the cell delay and output ramp for a cell instance are obtained from interpolation (or extrapolation, if the input ramp and/or output load are outside the range of the indices) of the table values.